Field-effect transistors (FETs), such as finFET devices, have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area overlying a substrate. However, as circuits are scaled to smaller dimensions and thus a smaller area, the lateral spacing between adjacent vertical fins may become too small to enable the vertical finFET devices to be formed properly. One reason for this is that it may be difficult to form the desired metal thicknesses between the adjacent fins along the height of the vertical fins.